Semiconductor technology has been continuously moving toward smaller process nodes following the Moore's law. Devices with powerful functions have been manufactured, although the semiconductor manufacturing becomes more and more difficult. Photolithography is the most critical production line in semiconductor manufacturing process. With the continuous reduction of semiconductor process nodes, the existing light-sources used in lithography technology are unable to meet the needs of semiconductor manufacturing. Extreme ultraviolet (EUV) lithography technology, multi-beam maskless technology, and nano-imprint technology have become hot focus for next generation lithography technology, although they have their own shortcomings and drawbacks, and still need to be improved.
When the Moore's law irreversibly continues to extend the footsteps, double-patterning (DP) technology becomes one of the best choices in semiconductor industry. With minimum changes based on existing lithography facilities, the DP technology can effectively fill the technical gap required for smaller nodes in the field of lithography and also improve the minimum pitch between adjacent semiconductor patterns. The principle of DP technology is to break down a set of high-density patterns into two independent sets of low-density patterns, and then fabricate them in a wafer. Currently, the DP technology includes self-aligned double-patterning (SADP) process, litho-etch-litho-etch (LELE) process, etc. Because the SADP process is less complex and less costly, the SADP process is frequently adopted in the formation of semiconductor devices.
However, when a substrate is etched using an existing DP process, the quality of the target pattern formed after the etching process may be undesirable, which may further affect the performance and the yield of the formed semiconductor structure. The disclosed semiconductor structures and fabrication methods thereof are directed to solve one or more problems set forth above and other problems in the art.